GlobalSpec

Appendix 1: CMOS Process Flow

Starting material p-type substrate or p epi on p + substrate for latch-up prevention (Taur et al., 1984). Grow pad oxide. Deposit CVD (Chemical Vapor Deposition) nitride. (See Fig. A1.1.) FIGURE A1.1 ...
GlobalSpec

CMOS Process Flow

Description: applications, such as medical devices, diagnostic equipment or process control. The essential goal is to understand the requirements of our customers and to implement the key benefits of ...
Electronics Weekly

LETI integrates III-V lasers on 200mm wafers using CMOS flow

Leti has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
EDN

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...
Design-Reuse

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...